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Critical Failure on Anlogic TD based FPGA with Murax

Status: Open.

#482 In SpinalHDL/VexRiscv;

· briansune opened on Aug 28, 2026

Question about EmbeddedRiscvJtag, DebugPlugin, and OpenOCD debugging via Xilinx BSCANE2

Status: Open.

#479 In SpinalHDL/VexRiscv;

· Usutatsu opened on Aug 5, 2026

Questions: APB3 ArrayBuffer via Apb3Decoder & CPU M plugin

Status: Open.

#477 In SpinalHDL/VexRiscv;

· briansune opened on Jun 1, 2026

Question and puzzling about prebuilt Hex under resource folder for Murax demo

Status: Open.

#476 In SpinalHDL/VexRiscv;

· briansune opened on May 23, 2026

share Risc-V knowledge for Future Digital Civilization Technology

Status: Open.

#474 In SpinalHDL/VexRiscv;

· fatalfeel opened on May 3, 2026

Assertion with configuration

Status: Open.

#473 In SpinalHDL/VexRiscv;

· RossComputerGuy opened on Mar 8, 2026

How do I add VexRiscv as a dependency in a mill project

Status: Open.

#472 In SpinalHDL/VexRiscv;

· parthkalgaonkar opened on Mar 1, 2026

What is the cycle latency of VexRiscv FPU double‑precision add (FADD.D), and how can I derive it from the RTL/config?

Status: Open.

#469 In SpinalHDL/VexRiscv;

· Usutatsu opened on Jan 22, 2026

[Bug] CSR writes to cycle/instret do not raise illegal-instruction

Status: Open.

#465 In SpinalHDL/VexRiscv;

· canxin121 opened on Nov 24, 2025

[Bug] VexRiscv FSGNJX.D Sign Bit Wrong

Status: Open.

#464 In SpinalHDL/VexRiscv;

· canxin121 opened on Nov 24, 2025

How to add RV32IMAF instructions to a modified Murax SoC?

Status: Open.

#461 In SpinalHDL/VexRiscv;

· Usutatsu opened on Nov 13, 2025

Briey Soc + HDMI +SD_card

Status: Open.

#460 In SpinalHDL/VexRiscv;

· Nauqchix opened on Nov 13, 2025